Field of the Invention
This invention relates to a process for the production of semiconductor devices. In particular, this invention relates to a process for the production of semiconductor devices which comprise a single-crystalline layer of silicon, as an active layer, on a single-crystalline layer of insulating materials such as magnesia spinel (MgO.multidot.Al.sub.2 O.sub.3) and sapphire (.alpha.-Al.sub.2 O.sub.3). Such an active silicon layer on an insulator or insulating layer is generally referred to in the art as an SOI (silicon-on-insulator), and is used for fabrication of bipolar transistors, metal-oxide semiconductor (MOS) devices, high-voltage bipolar integrated circuits (IC's), or similar circuits and devices.
Description of the Related Art
Many types of SOI's have been proposed and used in the production of semiconductor devices due to the advantages offered by the same. First, they do not necessitate isolation in the devices or, even if isolation is necessary, it is easy to form an isolation area. Further, semiconductor devices having SOI structures show no or little parasitic capacitance. These remarkable advantages ensure the production of semiconductor devices having a high quality and integrity.
A typical example of the prior art SOI structure can be found in FIGS. 1a and 1b. As illustrated in FIG. 1a, the SOI material comprises a (100) Si substrate 1 having deposited thereon an SiO.sub.2 layer 2 and an amorphous Si layer 3. The amorphous Si layer 3 is generally formed by using vapor phase epitaxy (VPE) or other techniques.
In order to convert amorphous Si in the layer 3 to single-crystalline Si, the material is annealed at a temperature of about 600.degree. C. to 1100.degree. C. Crystallization of the amorphous Si is started at an exposed portion of the Si substrate 1, as is shown in FIG 1b. Namely, the exposed portion of the substrate 1 acts as a seed for crystallization. The single-crystalline Si area 4 gradually extends over the layer 3. Finally, all of the amorphous Si in the layer 3 is converted to a single-crystalline form of silicon.
The result is shown in FIG. 2, which is a schematic plan view of the resulting SOI structure. Unexpectedly, the single-crystalline Si layer 4 has partially formed (110) and (111) crystal structures in addition to the (100) crystal structure. This means that the layer 4 is not a single-crystalline form, but polycrystalline form. Such an undesirable result can be frequently encountered in the formation of the illustrated SOI structure.
Heteroepitaxy is also well-known and widely used in the formation of SOI structures. As we have already reported in, for example, M. Ihara et al., "Vapor phase epitaxial growth of MgO.multidot.Al.sub.2 O.sub.3 ", J. Electrochem. Soc., Vol. 129, No. 11, pp. 2569-2573, Nov. 1982, and M. Ihara, "Epitaxial spinel growth for integrated circuits", Microelectronic Engineering, Vol. 1, pp. 161-177, 1983, SOI structures produced by using heteroepitaxy or the heteroepitaxial growth technique have many advantages. For example, the resulting active Si layers on sapphire or spinel show high quality and mobility. High voltage isolation can be achieved. The large-sized Si wafers can be used as the substrate, therefore low-price devices can be produced.
However, this technique suffers from a drawback that the active Si layers have unavoidable stacking faults due to their heterojunction with the underlying sapphire or spinel layer. This defect will become clearer with reference to FIG. 3, which illustrates a typical Si-on-spinel (MgO.multidot.Al.sub.2 O.sub.3)-on-Si double heterostructure.
In FIG. 3, the illustrated SOI structure comprises a (100) single-crystalline Si substrate 1 having deposited thereon a (100)--oriented spinel epitaxial layer 5 and (100)-oriented single-crystalline Si layer 6. The Si layer 6 is generally deposited by VPE. During the VPE process, stacking faults (111) are induced in the growing Si layer 6. We found that the formation of the stacking faults is started at limited portions of the Si/spinel interface, each of which acts as a core of the fault formation during crystal growth. Such core portions are considered to be due to the about 0.8% lattice mismatch between Si and spinel.
The stacking faults result in conspicuous straight defects on a surface of the active Si layer after they have passed through the layer. This means lowering of the yield of the SOI structure and, accordingly, the finally produced devices. It is, therefore, desirable to provide improved methods for forming SOI structures which have thin or thick layers of single-crystalline Si with high quality and without stacking faults, on an insulating layer of spinel, sapphire, or other single crystals.